The present disclosure relates generally to lamp ballasts and associated methods of operation. More particularly, the present disclosure pertains to a buck inverter topology for a high-intensity discharge (HID) lamp ballast and associated control methods to regulate an open circuit voltage and further prevent current flow through the inverter from being continuous regardless of an operating mode.
The open circuit voltage (OCV) for a high-intensity discharge lamp ballast is generally known in the art to be a primary design parameter. If the OCV is higher than that specified by a lamp manufacturer, lamp stem arcing may occur as a result. If the OCV is lower than that specified, the lamp may not start correctly and shorter lamp life may be another result.
In one method for addressing the OCV design requirements as conventionally known for a low-frequency, square wave HID lamp ballast, a single switch buck regulator is provided in a cascade arrangement with a full bridge, low frequency DC-AC power inverter. The single switch buck regulator regulates its output DC voltage to meet the OCV specification, and the DC-AC inverter follows up by inverting the regulated DC voltage from the single switch buck regulator to a low frequency, square wave AC voltage. In a no-load condition, such as where there is no lamp physically present across lamp output terminals or where a lamp is physically present but has not been ignited, this low frequency, square wave voltage is open circuit voltage (OCV).
There are known advantages and disadvantages for the configuration discussed above. For example, the configuration allows for easy control of the OCV because the buck regulator is separated from the low-frequency DC-AC square wave inverter, and further allows for easy control of lamp power by the buck regulator itself. During a lamp ignition operation, the buck regulator operates in a fixed-frequency discontinuous conduction mode. During lamp run-up operation, the buck regulator operates in continuous conduction mode (i.e., the inductor current flows continuously and never goes to zero) because the lamp voltage is very low. During normal (also referred to as steady-state) lamp operation, the buck regulator operates in either a fixed-frequency discontinuous mode or a variable-frequency critical discontinuous conduction mode to maximize circuit efficiency.
However, the cost of such a design is relatively high because the configuration needs five switches to implement the stated operations. Also, during lamp run-up operations the circuit is in continuous mode, which lowers the circuit efficiency. In some circumstances the lamp may remain in a run-up operation for an extended period of time, and care must accordingly be taken to dissipate heat from the buck switch and/or other power devices.
Another common configuration, such as for example an HID lamp ballast 1 as shown in FIG. 1, is to provide a buck DC-AC inverter 1 having four switches Q1 to Q4 arranged in a full bridge configuration between positive and negative inverter rails 24, 26 for regulating power to an HID lamp. A buck capacitor C1 and a buck inductor L1 are coupled in series between output terminals for the switches, or in other words between a first node between switches Q1, Q2 and a second node between switches Q3, Q4. An ignition circuit 12 is also coupled on a first end to the node between switches Q1, Q2. A first lamp output terminal X1 is coupled to a second end of the ignition circuit 12 and a second lamp output terminal X2 is coupled to a node between the buck capacitor C1 and the buck inductor L1. A current sensor 16 is provided, in the example shown a resistor R1 coupled to the negative rail 26. A control circuit 14 receives feedback inputs from the inverter 10 and provides control signals to the switches Q1-Q4 via switch drivers 15a, 15b. 
The control circuit 14 in the example shown includes a turn-off detection circuit 18 arranged to detect a peak current via the current sensor 16, a turn-on detection circuit 20 (i.e., edge detection circuit) arranged to detect positive/rising edges and negative/falling edges of a voltage waveform at the second node between switches Q3, Q4, and a logic control flip-flop 22 or equivalent circuitry to receive outputs from the turn on detection circuit 20 and the turn off detection circuit 18 and provide appropriate signals to the switch drivers 15a, 15b. 
One primary shortcoming of the conventional configuration shown in FIG. 1 is that the open circuit voltage is not regulated. In other words, the open circuit voltage is equivalent to the voltage V_c1 across the buck capacitor C1 and as shown further has the same value (VDC) as that provided on the positive rail 24. The range of the positive DC rail voltage is largely restricted by the input line voltage or the front-end power factor correction circuit.
Referring to FIG. 2, the voltage V_c1 across the buck capacitor C1 is shown during a no-load condition. The voltage V_c1 across the buck capacitor C1 changes in polarity at a low frequency. The absolute peak of the buck capacitor voltage V_c1 is substantially the same as the voltage VDC on the positive rail 24.